This invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device having a redundancy circuit.
In recent years, a semiconductor element is miniaturized and a semiconductor device is increased in scale. In particular, such trend is prominent in the field of a semiconductor memory device. For example, in a dynamic random access memory (DRAM), a product having a memory capacity of 1 Gbit is developed and put into practical use.
Such semiconductor memory device has a main memory cell array region in which a normal memory cell array is arranged and a relieving redundancy memory cell array region in which a spare memory cell array is arranged. The semiconductor memory device is provided with a redundancy circuit for replacing, in case where a defective memory is found at a part of the main memory cell array region, the defective memory by a redundancy memory cell. By the use of the redundancy circuit, the semiconductor memory device having a large scale is improved in yield and lowered in cost.
The redundancy circuit comprises a redundancy memory cell array section and a redundancy replacement judging circuit for judging whether or not the defective memory is replaced by the redundancy memory cell. The redundancy replacement judging circuit comprises a fuse section storing an address of the defective memory in the main memory cell array, a fuse judging circuit for comparing the address programmed in the fuse section and an input address and judging coincidence or incoincidence between these addresses to produce a judgment result, a logic section for carrying out logical operation upon the judgment result, and an output section.
When the input address is coincident with the address programmed in the fuse section, the redundancy circuit judges that the defective memory is replaced by the redundancy memory cell. Then, access to a memory cell in the main memory cell array region is inhibited. Instead, the redundancy memory cell in the redundancy memory cell array region is accessed and a reading or a writing operation is performed. On the other hand, if the input address is not coincident with the address stored in the fuse section, no replacement is carried out. Then, a memory cell in the main memory cell array region is accessed and a reading or a writing operation is performed.
For the redundancy circuit, various improvements have been made. For example, Japanese Unexamined Patent Application Publication (JP-A) No. 2001-35187 discloses a semiconductor memory and a redundancy relieving method thereof. According to the technique disclosed in the publication, in a probe inspection preceding redundancy relief, a pseudo relief information circuit is supplied with a defect address upon detection of a defect in a normal memory cell and a redundancy cell is selected. In this manner, a pseudo relieved state equivalent to a relieved state is tested so that the number of times of probe tests is reduced. Japanese Unexamined Patent Application Publication (JP-A) No. 2002-42486 discloses a semiconductor memory in which an internal power source voltage generating circuit is enhanced in current supply ability only upon programming a fuse. Thus, it is attempted to efficiently save current consumption.
Japanese Unexamined Patent Application Publication (JP-A) No. 2004-13985 discloses a semiconductor storage device provided with a redundancy function and a method of reducing current consumption therein. Specifically, the current consumption is reduced by inhibiting precharge of a bit line connected to a memory cell judged defective and an unused redundancy cell. Japanese Unexamined Patent Application Publication (JP-A) No. 2004-178674 discloses a semiconductor memory using an inexpensive tester having no FAM (Fail Address Map). The semiconductor memory comprises a built-in comparator circuit for comparing data from a memory cell and an expected value supplied from the tester so that a defective cell is detected and relieved.
On the other hand, the semiconductor memory device is required to have a higher operation frequency following an increase in operation speed of a CPU or the like. In order to achieve a higher data transfer speed, the redundancy circuit must have a higher operation speed. In particular, the redundancy replacement judging circuit of the redundancy circuit must be increased in operation speed.
Referring to FIGS. 1 and 2, description will be made of a related redundancy replacement judging circuit. As illustrated in FIG. 1, the redundancy replacement judging circuit comprises first through m-th fuse judging circuit groups 1 to m. The first through the m-th fuse judging circuit groups 1 to m comprise fuse judging circuits (11 to 1n, 21 to 2n, . . . , m1 to mn) having fuses, respectively. Each of the fuse judging circuits is supplied with a fuse judgment start signal and produces a fuse judgment signal. The fuse judgment signals are supplied to first through m-th NOR circuits 201 to 20m corresponding to the first through the m-th fuse judging circuit groups 1 to m, respectively. Each of the first through the m-th NOR circuits 201 to 20m produces a fuse group judgment signal.
The fuse group judgment signals from the first through the m-th NOR circuits 201 to 20m are supplied to an OR circuit 30. The OR circuit 30 produces a redundancy replacement judgment signal which is delivered to a judgment result release circuit 70. The judgment result release circuit 70 produces a redundancy enable signal (which may also be called a redundancy judgment signal). The fuse judgment start signal is supplied from a judgment control circuit 80 to each of the fuse judging circuits and to an inverter delay circuit 90. The inverter delay circuit 90 delays the fuse judgment start signal to produce a delayed fuse judgment start signal which is supplied to the judgment result release circuit 70.
Next, an operation of the redundancy replacement judging circuit will be described. Each of the fuse judging circuits is supplied with the fuse judgment start signal from the judgment control circuit 80 and judges coincidence or incoincidence between fuse programmed information and input information. Each of the fuse judging circuits (11 to 1n, 21 to 2n, . . . , m1 to mn) produces the fuse judgment signal having a low level and a high level upon coincidence and incoincidence between the programmed information in the fuse and the input information, respectively, and delivers the fuse judgment signal to a corresponding one of the first through the m-th NOR circuits 201 to 20m. 
The fuse judgment signals produced by the fuse judging circuits 11 to 1n of the first fuse judging circuit group 1 are supplied to the first NOR circuit 201. Similarly, the fuse judgment signals produced by the fuse judging circuits k1 to kn of the k-th fuse judging circuit group k are supplied to the k-th NOR circuit 20k. The first through the m-th NOR circuits 201 to 20m produce the fuse group judgment signals, respectively.
For example, if the input information supplied to the first fuse judging circuit group 1 is entirely coincident with the programmed information in the fuses, all of the fuse judging circuits 11 to in produce the fuse judgment signals of a low level and the first NOR circuit 201 produces the phase group judgment signal of a high level. On the other hand, incoincidence is judged at any of the fuse judging circuits in each of the second through the m-th fuse judging circuit groups 2 to m. Therefore, the second through the m-th NOR circuits 202 to 20m produce the fuse group judgment signals of a low level.
If the fuse group judgment signal produced by the first fuse judging circuit group 1 has a high level, a memory cell array at an input address is replaced by a redundancy memory cell corresponding to the first fuse judging circuit group 1. On the other hand, if the fuse group judgment signal produced by the first fuse judging circuit group 1 has a low level, the memory cell array at the input address is not replaced by the redundancy memory cell array corresponding to the first fuse judging circuit group 1.
Further, the OR circuit 30 is supplied with the fuse judgment signals from the second through the m-th NOR circuits 202 to 20m and produces the redundancy replacement judgment signal. The redundancy replacement judgment signal is a judgment signal representing whether or not the memory cell array at the input address is replaced by the redundancy memory cell. If the memory cell array is replaced by the redundancy memory cell, the fuse group judgment signal of one of the second through the m-th NOR circuits 202 to 20m has a high level and the OR circuit 30 produces the redundancy replacement judgment signal of a high level.
Supplied with the redundancy replacement judgment signal, the judgment result release circuit 70 produces a redundancy enable signal in synchronism with the delayed fuse judgment start signal. When the redundancy enable signal has a high level, the memory cell array is replaced by the redundancy memory cell. Then, the redundancy enable signal inhibits access to the normal main memory cell array and allows access to the redundancy memory cell array. On the contrary, if the redundancy enable signal has a low level, the memory cell array is not replaced by the redundancy memory cell. The redundancy enable signal allows access to the normal main memory cell array and inhibits access to the redundancy memory cell array.
Referring to FIG. 2, waveforms of the above-mentioned signals are shown. Specifically, these waveforms represent the fuse judgment start signal (a), the fuse judgment signal (b), the fuse group judgment signal (c), the redundancy replacement judgment signal (d), the delayed fuse judgment start signal (e), and the redundancy enable signal (f).
At first, the fuse judgment start signal (a) is turned to a high level. Comparison between the programmed information in the fuse and the input information is carried out and judgment is made. The fuse judgment signals (b) from the fuse judging circuits 11 to mn are supplied to the NOR circuits 201 to 20m corresponding to the respective fuse judging circuit groups. The NOR circuits 201 to 20m delivers the fuse group judgment signals (c) for the fuse judging circuit groups 1 to m to the OR circuit 30. The OR circuit 30 delivers the redundancy replacement judgment signal (d) to the judgment result release circuit 70.
The judgment result release circuit 70 is also supplied with the delayed fuse judgment start signal (e) and produces the redundancy enable signal (f) which is sent to an internal circuit (not shown). Thus, the internal circuit is controlled so as to operate the redundancy memory cell or the normal main memory cell array.
Herein, the delayed fuse judgment start signal has a delay time td which is determined by including a delay (or a delay time) of the fuse judgment start signal at the logic circuits and an operation margin Δt at the judgment result release circuit 70. The delay (or the delay time) td is very large and inhibits a high speed operation of the semiconductor memory device.
The reason will be described. The redundancy replacement judging circuit requires large current consumption during operation and transitional noise is generated at a power source and a GND line disposed near the redundancy replacement judging circuit. Further, a processing time from the input of the judgment start signal into the fuse judging circuit to the output of the judgment result and a processing time from the input of the judgment result into the logic circuits to the output of the result of logical operation are affected by the noise at the power supply and the GND line and depend upon a power source voltage and a temperature.
In case where the redundancy enable signal is released to an inside of a chip after the output of the logic circuit is produced, the inverter delay circuit 90 is provided to delay the release of the redundancy enable signal until an arrival time of the output of the logic circuit. This is because, if the release of the redundancy enable signal is performed before arrival of the output of the logic circuit in an output section of the judgment result release circuit 70, an error is released. In this case, because of the influence of the noise at the power source and the GND line as well as the dependency upon the power source voltage and the temperature, the delay time must include a wide margin in order to assure a sufficient waiting time during which the release is delayed by the inverter delay circuit. As a consequence, the time instant when the redundancy judgment result is released to the inside of the chip is delayed so that a high-speed access operation is inhibited.
As described above, the time instant when the redundancy judgment result (redundancy enable signal) is released to the inside of the chip is delayed so that a high-speed access operation is inhibited. In view of the above, it is desired to release the redundancy judgment result to the inside of the chip as fast as possible. However, the above-referenced publications merely propose an increase in efficiency of the redundancy circuit and a reduction in current consumption and do not mention an increase in operation speed of the redundancy circuit.